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ADT7411 a rev. prg 01/?03 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: ht tp://www.analog.com fax: 781/326-8703 analog devices, inc., 2003 spi/i 2 c ? ? ? ? ? compatible, 10-bit digital temperature sensor and eight channel adc preliminary technical data preliminary technical data i 2 c is a registered trademark of philips corporation spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation. the ADT7411 is protected by the following u.s. patent numbers and by other intellectual property rights : 6,169,442 6,097,239 us patent pending 5,867,012 5, 764174 functional block diagram features 10-bit temperature to digital converter 10-bit eight channel adc : dc input bandwidth input range: 0 v to 2.25 v and 0 v to v dd temperature range: -40 o c to +125 o c temperature sensor accuracy of 0.5 o c supply range : + 2.7 v to + 5.5 v power-down current 1 a internal 2.25 v ref option double-buffered input logic i 2 c ? ? ? ? ? , spi tm , qspi tm , microwire tm and dsp-compatible 4- wire serial interface 16-lead qsop package applications portable battery powered instruments personal computers smart battery chargers telecommunications systems electronic test equipment domestic appliances process control general description the ADT7411 combines a 10-bit temperature-to-digital converter and a 10-bit eight channel adc, in a 16-lead qsop package. this includes a bandgap temperature sensor and a 10-bit adc to monitor and digitize the tem- perature reading to a resolution of 0.25 o c. the ADT7411 operates from a single +2.7 v to + 5.5 v sup- ply. the input voltage range on the adc channels has a range of 0v to 2.25v and the input bandwidth is dc. the reference for the adc channels is derived internally. the ADT7411 provides two serial interface options, a four- wire serial interface which is compatible with spi tm , qspi tm , microwire tm and dsp interface standards; and a two-wire smbus/i 2 c interface. it features a standby mode that is controlled via the serial interface. the ADT7411?s wide supply voltage range, low supply current and spi/i 2 c-compatible interface, make it ideal for a variety of applications, including personal comput- ers, office equipment and domestic appliances. on-chip temperature sensor external temperature value register smbus/spi interface bus a-to-d converter internal temperature value register analog mux digital mux limit comparator digital mux address pointer register t high limit registers t low limit registers v dd limit registers control config. 1 register control config. 3 register control config. 2 register interrupt mask registers d+/ain1 cs scl/sclk sda/din dout/add int/int status registers v dd sensor v dd gnd ADT7411 d-/ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain high limit registers ain low limit registers v dd value register ain1 value register ain2 value register ain3 value register ain4 value register ain5 value register ain6 value register ain7 value register ain8 value register 9 7 8 14 1 2 16 15 6 5 4 13 12 11 10
? 2 ? rev. prg preliminary technical data ADT7411 ADT7411-specifications 1 (v dd =2.7 v to 5.5 v, gnd=0 v, unless otherwise noted) parameter 2 min typ max units cond itions/comments adc dc accuracy max v dd = 5 v resolution 10 bits integral nonlinearity 2 lsb differential nonlinearity 0.9 lsb offset error 2 % of fsr offset error match 0.5 lsb gain error 2 % of fsr gain error match 0.5 lsb adc bandwidth d c h z analog inputs input voltage range 0 2.25 v ain1 to ain8. c4 = 0 in control config. 3. 0v dd v ain1 to ain8. c4 = 1 in control config. 3. ain conversion time 712 s averaging (16 samples) on. 44.5 s averaging off. dc leakage current 1 a input capacitance tbd tbd p f input resistance tbd thermal characteristics internal reference used. averaging on. internal temperature sensor accuracy @ v dd =3.3v 10% 0.5 ct a = 40 c 0.5 2 ct a = 0 c to +85 c 2 3 ct a = -40 c to +125 c accuracy @ v dd =5v 5% 1 ct a = 40 c 2 3 ct a = 0 c to +85 c 3 4 ct a = -40 c to +125 c resolution 10 bits equivalent to 0.25 c long term drift 0.5 c/1000hrs conversion time 25.92 ms averaging (16 samples) on. 1.62 m s averaging off. external temperature sensor external transistor = 2n3906. accuracy @ v dd =3.3v 10% 1 ct a = 40 c 2 ct a = 0 c to +85 c. 3 ct a = -40 c to +125 c accuracy @ v dd =5v 5% 1.5 ct a = 40 c 2 3 ct a = 0 c to +85 c 3 4 ct a = -40 c to +125 c resolution 10 bits equivalent to 0.25 c conversion time 16.8 ms a veraging (16 samples) on. 1.05 ms averaging off. output source current 180 a h igh level 11 a low level round robin update rate 3 time to complete one measurement cycle. averaging on 32.33 ms pins 7 and 8 configured for ain1 and ain2 averaging off 2.02 ms pins 7 and 8 configured for ain1 and ain2 averaging on 47.7 ms pins 7 and 8 configured for d+ and d- averaging off 2.98 ms pins 7 and 8 configured for d+ and d- on-chip reference 4 reference voltage 2.25 v temperature coefficient 80 ppm/ c digital inputs 4 input current 1 a v in = 0v to v dd
ADT7411 ? 3 ? rev. prg preliminary technical data v il , input low voltage 0.8 v v ih , input high voltage 1.89 v pin capacitance 3 10 pf all digital inputs scl, sda glitch rejection 50 ns input filtering suppresses noise spikes of less than 50 ns digital output output high voltage, v oh 2.4 v i source = i sink = 200 a output low voltage, v ol 0.4 v i ol = 3 ma output high current, i oh 1mav oh = 5 v output capacitance, c out 50 pf int/ int output saturation voltage 0.8 v i out = 4 ma i 2 c timing characteristics 5,6 serial clock period, t 1 2.5 s fast-mode i 2 c. see figure 1 data in setup time to scl high, t 2 data out stable after scl low, t 3 0 ns see figure 1 sda low setup time to scl low (start condition), t 4 50 ns see figure 1 sda high hold time after scl high (stop condition), t 5 50 ns see figure 1 sda and scl fall time, t 6 90 ns see figure 1 spi timing characteristics 7, 8 cs to sclk setup time, t 1 0 ns see figure 2 sclk high pulsewidth, t 2 50 ns see figure 2 sclk low pulse, t 3 50 ns see figure 2 data access time after sclk falling edge, t 4 9 35 ns see figure 2 data setup time prior to sclk rising edge, t 5 20 ns see figure 2 data hold time after sclk rising edge, t 6 0 ns see figure 2 cs to sclk hold time, t 7 0 ns see figure 2 cs to dout high impedance, t 8 40 ns see figure 2 power requirements v dd 2.7 5.5 v v dd settling time 50 ms v dd settles to within 10% of it ? s final voltage level i dd (normal mode) 10 2mav dd = +3.3 v, v ih = v dd and v il = gnd 2.2 ma v dd = +5 v, v ih = v dd and v il = gnd i dd (power down mode) t b d 3 a v dd = +3.3 v, v ih =v dd and v il =gnd tbd 10 a v dd = +5 v, v ih =v dd and v il =gnd power dissipation tbd 6.6 w v dd = +3.3 v. using normal mode tbd 10 w v dd = +3.3 v. using shutdown mode notes: 1 temperature ranges are as follows: a version: -40 c to +125 c. 2 see terminology. 3 round robin is the continuous sequential measurement of the following channels : v dd , internal temperature, external temperature/ (ain1, ain2), ain3, ain4, ain5, ain6, ain7 and ain8. 4 guaranteed by design and characterization, not production tested 5 the sda & scl timing is measured with the input filters turned on so as to meet the fast-mode i 2 c specification. switching off the input filters improves the transfer rate but has a negative affect on the emc behaviour of the part. 6 guaranteed by design. not tested in production. 7 guaranteed by design and characterization, not production tested. 8 all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. 9 measured with the load circuit of figure 3. 10 i dd spec. is valid for fullscale analog input voltages. interface inactive. adc active. load currents excluded. specifications subject to change without notice. parameter 2 min typ max units cond itions/comments
? 4 ? rev. prg preliminary technical data ADT7411 t 1 t 2 t 3 t 5 d7 d in d6 d5 d4 d3 d2 d1 x x x x x x x d0 x sclk cs x d out xx x x x x d6 d5 d4 d3 d2 d1 d0 xd7 t 6 t 4 t 7 t 8 figure 3. load circuit for access time and bus relinquish time 1.6v i ol 200 a 200 a i ol to output pin c l 50pf figure 2. diagram for spi bus timing t 1 t 4 t 2 t 3 t 5 scl sda data in sda data out t 6 figure 1. diagram for i 2 c bus timing
ADT7411 ? 5 ? rev. prg preliminary technical data absolute maximum ratings* v dd to gnd ? 0.3 v to +7 v analog input voltage to gnd ? 0.3 v to v dd + 0.3 v digital input voltage to gnd ? 0.3 v to v dd + 0.3 v operating temperature range ? 40 c to +125 c storage temperature range ? 65 c to +150 c junction temperature +150 c 16-lead qsop package power dissipation 2 (t j max - t a ) / ja thermal impedance 3 ja junction-to-ambient 105.44 c/w jc junction-to-case 38.8 c/w ir reflow soldering peak temperature +220 c (-0/+5 c) time at peak temperature 10 to 20 secs ramp-up rate 2-3 c/sec ramp-down rate -6 c/sec notes: 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability. 2 values relate to package being used on a 4-layer board. 3 junction-to-case resistance is applicable to components featuring a preferential flow direction, eg. components mounted on a heat sink. junction-to-ambient resistance is more useful for air-cooled pcb- mounted components. ordering guide model temperature range package description package options ADT7411arq ? 40 c to +125 c 16-lead qsop rq-16 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADT7411 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recom- mended to avoid performance degradation or loss of functionality. warning! esd sensitive device pin configuration qsop table 1. i 2 c address selection add pin i 2 c address low 1001 000 float 1001 010 high 1001 011 ADT7411 top view (not to scale) ain6 gnd sda/din dout/add vdd d+/ain1 d-/ain2 cs scl/sclk 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 ain5 ain7 ain8 nc int/int ain3 ain4
? 6 ? rev. prg preliminary technical data ADT7411 ADT7411 pin function description pin mnemonic description 1 ain6 an alog input. single ended analog input channel. input range is 0 v to 2.25 v or 0 v to v dd . 2 ain5 an alog input. single ended analog input channel. input range is 0 v to 2.25 v or 0 v to v dd . 3 n c no connection to this pin. 4 cs spi - active low control input. this is the frame synchronization signal for the input data. when cs goes low, it enables the input register and data is transferred in on the rising edges and out on the falling edges of the subsequent serial clocks. it is recommended that this pin be tied high to v dd when operating the serial interface in i 2 c mode. 5 g n d ground reference point for all circuitry on the part. analog and digital ground. 6v dd positive supply voltage, +2.7 v to +5.5 v. the supply should be decoupled to ground. 7 d+/ain1 d+. positive connection to external temperature sensor. ain1. analog input. single ended analog input channel. input range is 0 v to 2.25 v or 0 v to 5 v. 8 d-/ain2 d-. negative connection to external temperature sensor. ain2. analog input. single ended analog input channel. input range is 0 v to 2.25 v or 0 v to 5 v. 9 ain3 an alog input. single ended analog input channel. input range is 0 v to 2.25 v or 0 v to v dd . 10 int/ int over limit interrupt. the output polarity of this pin can be set to give an active low or active high interrupt when temperature, v dd or ain limits are exceeded. default is active low. 11 dout/add spi serial data output. logic output. data is clocked out of any register at this pin. data is clocked out on the falling edge of sclk. open drain output - needs a pullup resistor. add - i 2 c serial bus address selection pin. logic input. a low on this pin gives the address 1001 000, leaving it floating gives the address 1001 010 and setting it high gives the address 1001 011. the i 2 c address set up by the add pin is not latched by the device until after this address has been sent twice. on the 8 th scl cycle of the second valid communication, the serial bus address is latched in. any subsequent changes on this pin will have no affect on the i 2 c serial bus address. 12 sda/din sda. i 2 c serial data input. i 2 c serial data to be loaded into the parts registers is provided on this input. din. spi serial data input. serial data to be loaded into the parts registers is provided on this input. data is clocked into a register on the rising edge of sclk. 13 scl/sclk serial cl ock input. this is the clock input for the serial port. the serial clock is used to clock data out of any register of the ADT7411 and also to clock data into any register that can be written to. 14 ain4 analog input. single ended analog input channel. input range is 0 v to 2.25 v or 0 v to v dd . 15 ain8 analog input. single ended analog input channel. input range is 0 v to 2.25 v or 0 v to v dd . 16 ain7 analog input. single ended analog input channel. input range is 0 v to 2.25 v or 0 v to v dd .
ADT7411 ? 7 ? rev. prg preliminary technical data terminology relative accuracy relative accuracy or integral nonlinearity (inl) is a mea- sure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the adc transfer function. typical inl versus code plot can be seen in tpc 4. differential nonlinearity differential nonlinearity (dnl) is the difference be- tween the m easured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. the adc is guaranteed monotonic by design. typical dnl versus code plot can be seen in tpc 3. offset error this is a measure of the offset error of the adc. it can be negative or positive. it is expressed in mv. offset error match this is the difference in offset error between any two channels gain error this is a measure of the span error of the adc. it is the deviation in slope of the actual adc transfer characteristic from the ideal expressed as a percentage of the full-scale range. gain error match this is the difference in gain error between any two chan- nels. offset error drift this is a measure of the change in offset error with changes in temperature. it is expressed in (ppm of full- scale range)/ c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full- scale range)/ c. long term temperature drift this is a measure of the change in temperature error with the passage of time. it is expressed in c/1000hrs. the concept of long-term stability has been used for many years to describe by what amount an ic ? s parameter would shift during its lifetime. this is a concept that has been typically applied to both voltage references and monolithic temperature sensors. unfortunately, integrated circuits cannot be evaluated at room temperature (25 c) for 10 years or so to determine this shift. as a result, manufactur- ers very typically perform accelerated life-time testing of integrated circuits by operating ics at elevated tempera- tures (between 125 c and 150 c) over a shorter period of time (typically, between 500 and 1000 hours). as a result of this operation, the lifetime of an integrated circuit is significantly accelerated due to the increase in rates of reaction within the semiconductor material. as a result of this operation, the lifetime of an integrated circuit is sig- nificantly accelerated due to the increase in rates of reac- tion within the semiconductor material. dc power-supply rejection ratio (psrr) this is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac while monitoring another dac. it is expressed in v. round robin this term is used to describe the ADT7411 cycling through the available measurement channels in sequence, taking a measurement on each channel.
? 8 ? rev. prg preliminary technical data ADT7411 tpc 3. adc dnl tpc 4. adc inl tpc 5. psrr vs supply ripple frequency tpc 6. temperature error @ 3.3 v and 5 v tpc 1. supply current vs. supply voltage tpc 2. power-down current vs. supply voltage title 0 0 0 00 0 t i t l e 0000 title 0 0 0 00 0 t i t l e 0000 title 0 0 0 00 0 t i t l e 0000 title 0 0 0 00 0 t i t l e 0000 title 0 0 0 00 0 t i t l e 0000 title 0 0 0 00 0 t i t l e 0000
ADT7411 ? 9 ? rev. prg preliminary technical data title 0 0 0 00 0 t i t l e 0000 tpc 7. adc offset error and gain error vs temperature title 0 0 0 00 0 t i t l e 0000 tpc 8. adc offset error and gain error vs v dd
? 10 ? rev. prg preliminary technical data ADT7411 ADT7411 operation directly after the power-up calibration routine the ADT7411 goes into idle mode. in this mode the device is not performing any measurements and is fully powered up. to begin monitoring, write to control configuration 1 (address = 18h) register and set bit c0 = 1. the ADT7411 goes into it ? s power-up default measurement mode, which is round robin. the device proceeds to take measurements on the v dd channel, internal temperature sensor channel, external temperature sensor channel or ain1 and ain2, ain3, ain4, ain5, ain6, ain7 and finally ain8 . once it finishes taking measurements on the ain8 channel the device immediately loops back to start taking measurements on the v dd channel and repeats the same cycle as before. this loop continues until the monitoring is stopped by resetting bit c0 of control con- figuration 1 register to 0. it is also possible to continue monitoring as well as switching to single channel mode by writing to control configuration 2 register (address = 19h) and setting bit c4 = 1. further explanation of the single channel and round robin measurement modes are given in later sections. all measurement channels have averaging enabled on them on power-up. averaging forces the device to take an average of 16 readings before giving a final measured result. to disable averaging and conse- quently decrease the conversion time by a factor of 16, set c5 = 1 in control configuration 2 register. there are eight single ended analog input channels on the ADT7411, ain1 to ain8. ain1 and ain2 are multi- plexed with the external temperature sensors d+ and d- terminals. bits c1 and c2 of control configuration 1 register (address = 18h) are used to select between ain1/ 2 and external temperature sensor. the input range on the analog input channels is dependent on whether the adc reference used is the internal v ref or v dd . to meet lin- earity specifications, it is recommended that the maximum v dd value is 5 v. bit c4 of control configuration 3 reg- ister is used to select between the internal reference or v dd as the analog inputs adc reference. the dual serial interface defaults to the i 2 c protocol on power-up. to select and lock in the spi protocol please follow the selection process as described in the serial interface selection section. the i 2 c protocol cannot be locked in, while the spi protocol on selection is automati- cally locked in. the interface can only be switched back to be i 2 c when the device is powered off and on. when using i 2 c the cs pin should be tied to either v dd or gnd. there are a number of different operating modes on the ADT7411 devices and all of them can be controlled by the configuration registers. these features consist of the int/ int pin, enabling and disabling interrupts, polarity of the int/ int pin, enabling and disabling the averaging on the measurement channels, smbus timeout and software reset. power-up calibration it is recommended that no communication to the part is initiated until approximately 5ms after v dd has settled to within 10% of it ? s final value. it is generally accepted that most systems take a maximum of 50ms to power-up. power-up time is directly related to the amount of decoupling on the voltage supply line. during this 5ms after v dd has settled, the part is perform- ing a calibration routine and any communication to the device will interrupt this routine and could cause errone- ous temperature measurements. if it not possible to have v dd at it ? s nominal value by the time 50ms has elapsed or that communication to the device has started prior to v dd settling then it is recommended that a measurement be taken on the v dd channel before a temperature measure- ment is taken. the v dd measurement is used to calibrate out any temperature measurement error due to different supply voltage values. functional description - analog inputs single-ended inputs the ADT7411 offers eight single-ended analog input channels. the analog input range is between 0 v to 2.25 v or 0 v to v dd . to maintain the linearity specification it is recommendated that the maximum v dd value be set at 5 v. selection between the two input ranges is done by bit c4 of control congifuration 3 register (address = 1ah). setting this bit to 0 sets up the analog input adc refer- ence to be sourced from the internal voltage reference of 2.25 v. setting the bit to 1 sets up the adc reference to be sourced from v dd . the adc resolution is 10 bits and is mostly suitable for dc input signals or very slow varying ac signals. bits c1:2 of control configuration 1 register (address = 18h) are used to set up pins 7 and 8 as ain1 and ain2. figure 4 shows the overall view of the eight channel analog input path. ain1 ain2 ain3 ain4 m u l t i p l e x e r 10-bit resist or-string adc to adc value re g ister ain5 ain6 ain7 ain8 figure 4. octal analog input path converter operation the analog input channels use a successive approximation adc based around a resistor-string dac. figures 6 and 7 show simplified schematics of the adc. figure 6 shows the adc during acquisition phase. sw2 is closed and sw1 is in position a. the comparator is held in a bal- anced condition and the sampling capacitor acquires the signal on ain.
ADT7411 ? 11 ? rev. prg preliminary technical data figure 5. signal conditioning for external diode temperature sensor ref in t v ref v dd ain ref / 2 compa rator control lo gic resistor-string da c sampling capacitor sw 1 sw2 acquisition phase a b figure 6. adc acquisition phase when the adc eventually goes into conversion phase, see figure 7, sw2 opens and sw1 moves to position b caus- ing the comparator to become unbalanced. the control logic and the dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the comparator is rebalanced the conversion is complete. the control logic generates the adc output code. figure 8 shows the adc transfer function for single-ended analog inputs. ref in t v ref v dd ain ref / 2 comparator control logic r es istor-s tring dac sa m pl in g ca pacito r sw 1 sw 2 conversion phase a b figure 7. adc conversion phase adc transfer function the output coding of the ADT7411 analog inputs is straight binary. the designed code transitions occur mid- way between successive integer lsb values (i.e. 1/2lsb, 3/2lsb, etc.). the lsb is v dd /1024 or int v ref /1024, int v ref = 2.25 v. the ideal transfer characteristic is shown in figure 8 below. 111...111 111...110 111...000 011...111 000...010 000...001 000...000 a d c c o d e 0v 1/2lsb +v ref -1lsb analog input 1lsb = int v ref /10 24 1lsb = v dd /1024 figure 8. transfer function v dd i nxi i bia s d+ d- remote sensing transistor (2n3906) lowpass filter f c = 65khz to ad c v out+ v out- bias diode c1 optional capacitor, up to 3nf max. can be added to improve high frequency noise rejection in noisy environments
? 12 ? rev. prg preliminary technical data ADT7411 to work out the voltage on any analog input channel, the following method can be used: 1 lsb = reference (v) / 1024 convert value read back from ain value register into decimal. ain voltage = ain value (d) x lsb size d = decimal example: internal reference used. therefore vref = 2.25 v. ain value = 512d 1 lsb size = 2.25 v / 1024 = 2.197x10 -3 ain voltage = 512 x 2.197x10 -3 = 1.125 v analog input esd protection figure 10 shows the input structure on any of the analog input pins that provides esd protection. the diode pro- vides the main esd protection for the analog inputs. care must be taken that the analog input signal never drops below the gnd rail by more than 200mv. if this happens then the diode will become forward biased and start con- ducting current into the substrate. the 4pf capacitor is the typical pin capacitance and the resistor is a lumped component made up of the on-resistance of the multi- plexer switch. 100 r 4pf ain figure 10. equivalent analog input esd circuit ain interrupts the measured results from the ain inputs are compared with the ain v high (greater than comparsion) and v low ( less than and equal to comparsion) limits. an interrupt occurs if the ain inputs exceed or equal the limit regis- ters. these voltage limits are stored in on-chip registers. please note that the limit registers are 8 bits long while the ain conversion result is 10 bits long. if the voltage limits are not masked out then any out of limit compari- sons generate flags that are stored in interrupt status 1 register (address = 00h) and one or more out-of limit results will cause the int/ int output to pull either high or low depending on the output polarity setting. it is good design practice to mask out interrupts for channels that are of no concern to the application. figure 11 showes the interrupt structure for the ADT7411. it gives a block diagram representation of how the various measurement channels affect the int/ int pin. functional description - measurement temperature sensor the ADT7411 contains an a-d converter with special input signal conditioning to enable operation with external and on-chip diode temperature sensors. when the ADT7411 is operating in single channel mode, the a to d converter continually processes the measurement taken on one channel only. this channel is preselected by bits c0:c3 in control configuration 2 register (address 19h). when in round robin mode the analog input multiplexer sequently selects the v dd input channel, on-chip tempera- ture sensor to measure its internal temperature, the exter- nal temperature sensor or an ain channel and then the rest of the ain channels. these signals are digitized by the adc and the results stored in the various value regis- ters. figure 9. top level structure of internal temperature sensor nxi i v dd i bia s to ad c v out+ v out- bias diode internal sense transistor
ADT7411 ? 13 ? rev. prg preliminary technical data the measured results from the temperature sensors are compared with the internal and external, t high , t low limits. these temperature limits are stored in on-chip registers. if the temperature limits are not masked out then any out of limit comparisons generate flags that are stored in interrupt status 1 register. one or more out-of limit results will cause the int/ int output to pull either high or low depending on the output polarity setting. theoretically, the temperature sensor and adc can mea- sure temperatures from -128 o c to +127 o c with a resolu- tion of 0.25 o c. however, temperatures outside t a are outside the guaranteed operating temperature range of the device. temperature measurement from -128 o c to +127 o c is possible using an external sensor. temperature measurement is initiated by three methods. the first method is applicable when the part is in single channel measurement mode. the temperature is measured 16 times and internally averaged to reduce noise. the total time to measure a temperature channel is typically 25.92ms (1.62ms x 16) for the internal temperature sensor and 16.8ms (1.05ms x 16) for the external temperature sensor. the new temperature value is loaded into the temperature value register and ready for reading by the i 2 c or spi interface. the user has the option of disabling the averaging by setting a bit (bit 5) in the control con- figuration register 2 (address 19h). the ADT7411 de- faults on power-up with the averaging enabled. the second method is applicable when the part is in round robin measurement mode. the part measures both the internal and external temperature sensors as it cycles through all possible measurement channels. the two tem- perature channels are measured each time the part runs a round robin sequence. in round robin mode the part is continuously measuring all channels. temperature measurement is also initiated after every read or write to the part when the part is in either single chan- nel measurement mode or round robin measurement mode. once serial communication has started, any conver- sion in progress is stopped and the adc reset. conversion will start again immediately after the serial communica- tion has finished. the temperature measurement proceeds normally as described above. v dd monitoring the ADT7411 also has the capability of monitoring it ? s own power supply. the part measures the voltage on it ? s v dd pin to a resolution of 10 bits. the resultant value is stored in two 8-bit registers, the two lsbs stored in regis- ter address 03h and the eight msbs are stored in register address 06h. this allows the user to have the option of just doing a one byte read if 10-bit resolution is not important. the measured result is compared with v high and v low limits. if the v dd interrupt is not masked out then any out- of-limit comparison generates a flag in interrupt status 2 register and one or more out-of-limit results will cause the int/ int output to pull either high or low depending on the output polarity setting. measuring the voltage on the v dd pin is regarded as monitoring a channel along with the internal, external and ain channels. you can select the v dd channel for single channel measurement by setting bit c4 = 1 and setting bit c0 to bit c 2 to all 0 ? s in control configura- tion 2 register. figure 11. ADT7411 interrupt structure control configuration register 1 interrupt mask registers status bits interrupt status register 1 (temp and ain1 to ain4) watchdog limit comparisons external temp v dd diode fault ain1-ain4 ain5-ain8 int/int enable bit int/int (latched output) read reset s/w reset status bits interrupt status register 2 (v dd and ain5 to ain8) internal temp
? 14 ? rev. prg preliminary technical data ADT7411 when measuring the v dd value the reference for the adc is sourced from the internal reference. table 2 shows the data format. as the max v cc voltage measurable is 7 v, internal scaling is performed on the v cc voltage to match the 2.25v internal reference value. below is an example of how the transfer function works. v dd = 5 v adc reference = 2.25 v 1 lsb = adc reference / 2^10 = 2.25 / 1024 = 2.197mv scale factor = fullscale v cc / adc reference = 7 / 2.25 = 3.11 conversion result = v dd / ((7/scale factor) x lsb size) = 5 / (3.11 x 2.197mv) = 2dbh table 2. v dd data format, v ref = 2.25 v v dd value digital output binary hex 2.5 v 01 0110 1110 16e 2.7 v 01 1000 1011 18b 3 v 01 1011 0111 1b7 3.5 v 10 0000 0000 200 4 v 10 0100 1001 249 4.5 v 10 1001 0010 292 5 v 10 1101 1011 2db 5.5 v 11 0010 0100 324 6 v 11 0110 1101 36d 6.5 v 11 1011 0110 3b6 7 v 11 1111 1111 3 f f on-chip reference the ADT7411 has an on-chip 1.125 v band-gap refernece which is gained up by a switched capacitor amplifier to give an output of 2.25 v. the amplifier is powered up for the duration of the device monitoring phase and is pow- ered down once monitoring is disabled. this saves on current consumption. on power-up the default mode is to have the internal reference selected as the reference for the adc. the internal reference is always used when measur- ing v dd , the internal and external temperature sensors. round robin measurement on power-up the ADT7411 goes into round robin mode but monitoring is disabled. setting bit c0 of configura- tion register 1 to a 1 enables conversions. it sequences through all the available channels taking a measurement from each in the following order of v dd , internal tem- perature sensor, external temperature sensor/(ain1 and ain2), ain3, ain4, ain5, ain6, ain7 and ain8. pin 7 and pin 8 can be configured to be either external tem- perature sensor pins or stand alone analog input pins. once conversion is completed on the ain8 channel, the device loops around for another measurement cycle. this method of taking a measurement on all the channels in one cycle is called round robin. setting bit 4 of control configuration 2 (address 19h) disables the round robin mode and in turn sets up the single channel mode. the single channel mode is where only one channel, eg. inter- nal temperature sensor, is measured in each conversion cycle. the time taken to monitor all channels will normally not be of interest, as the most recently measured value can be read at any time. for applications where the round robin time is impor- tant, it can be easily calculated. as mentioned previously a conversion on the internal tem- perature channel takes 25.92 ms, on the external tempera- ture channel it takes 16.8ms, on the v dd and ain channels it takes 712 us. these values are typical times and the channels have averaging on. this means that each channel is measured 16 times and internally averaged to reduce noise. the total cycle time for v dd , ain1 to ain8 and internal temperature is therefore nominally : 712s + (8 x 712s) + 25.92ms = 32.33 ms the total cycle time with averaging off is: 32.33 ms / 16 = 2.02 ms the total cycle time for v dd , ain3 to ain8, internal temperature and external temperature is therefore nomi- nally : 712s + (6 x 712s) + 25.92ms + 16.8ms = 47.7 ms the total cycle time with averaging off is: 47.7 ms / 16 = 2.98 ms single channel measurement setting c4 of control configuration 2 register enables the single channel mode and allows the ADT7411 to focus on one channel only. a channel is selected by writing to bits c0:c3 in register control configuration 2 register. for example, to select the v dd channel for monitoring write to the control configuration 2 register and set c4 to 1 (if not done so already), then write all 0 ? s to bits c0 to c3 . all subsequent conversions will be done on the v dd channel only. to change the channel selection to the internal temperature channel, write to the control con- figuration 2 register and set c0 = 1. when measuring in single channel mode, conversions on the channel selected occur directly after each other. any communication to the ADT7411 stops the conversions but they are restarted once the read or write operation is completed. measurement method internal temperature measurement the ADT7411 contains an on-chip bandgap temperature sensor, whose output is digitized by the on-chip adc. the temperature data is stored in the internal tempera-
ADT7411 ? 15 ? rev. prg preliminary technical data ture value register. as both positive and negative tem- peratures can be measured, the temperature data is stored in two's complement format, as shown in table 3. the thermal characteristics of the measurement sensor could change and therefore an offset is added to the measured value to enable the transfer function to match the thermal characteristics. this offset is added before the temperature data is stored. the offset value used is stored in the inter- nal temperature offset register. external temperature measurement the ADT7411 can measure the temperature of one exter- nal diode sensor or diode-connected transistor. the forward voltage of a diode or diode-connected tran- sistor, operated at a constant current, exhibits a negative temperature coefficient of about -2mv/ o c. unfortunately, the absolute value of v be , varies from device to device, and individual calibration is required to null this out, so the technique is unsuitable for mass-production. the time taken to measure the external temperature can be reduced by setting c0 of control config. 3 register (1ah). this increases the adc clock speed from 1.4khz to 22khz but the analog filters on the d+ and d- input pins are switched off to accommodate the higher clock speeds. running at the slower adc speed, the time taken to measure the external temperature is tbd while on the fast adc this time is reduced to tbd. the technique used in the ADT7411 is to measure the change in v be when the device is operated at two different currents. this is given by: ? v be = kt/q x ln(n) where: k is boltzmann ? s constant q is charge on the carrier t is absolute temperature in kelvins n is ratio of the two currents figure 5 shows the input signal conditioning used to mea- sure the output of an external temperature sensor. this figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some micropro- cessors, but it could equally well be a discrete transistor. if a discrete transistor is used, the collector will not be grounded, and should be linked to the base. if a pnp transistor is used the base is connected to the d- input and the emitter to the d+ input. if an npn transistor is used, the emitter is connected to the d- input and the base to the d+ input. we recommend that a 2n3906 be used as the external transistor. to prevent ground noise interfering with the measure- ment, the more negative terminal of the sensor is not ref- erenced to ground, but is biased above ground by an internal diode at the d- input. as the sensor is operating in a noisy environment, c1 is provided as a noise filter. see the section on layout considerations for more informa- tion on c1. to measure ? v be , the sensor is switched between operating currents of i and n x i. the resulting waveform is passed through a lowpass filter to remove noise, thence to a chop- per-stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a dc voltage proportional to ? v be . this voltage is mea- sured by the adc to give a temperature output in 10-bit two ? s complement format. to further reduce the effects of noise, digital filtering is performed by averaging the re- sults of 16 measurement cycles. layout considerations digital boards can be electrically noisy environments, and care must be taken to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. the following precautions should be taken: 1. place the ADT7411 as close as possible to the remote sensing diode. provided that the worst noise sources such as clock generators, data/address buses and crts are avoided, this distance can be 4 to 8 inches. 2. route the d+ and d- tracks close together, in parallel, with grounded guard tracks on each side. provide a ground plane under the tracks if possible. 3. use wide tracks to minimize inductance and reduce noise pickup. 10 mil track minimum width and spacing is recommended. gnd d+ d- gnd 10 mil. 10 mil. 10 mil. 10 mil. 10 mil. 10 mil. 10 mil. figure 12. arrangement of signal tracks 4. try to minimize the number of copper/solder joints, which can cause thermocouple effects. where copper/ solder joints are used, make sure that they are in both the d+ and d- path and at the same temperature. thermocouple effects should not be a major problem as 1 o c corresponds to about 240v, and thermocouple voltages are about 3v/ o c of temperature difference. unless there are two thermocouples with a big tempera- ture differential between them, thermocouple voltages should be much less than 200mv. 5. place 0.1f bypass and 2200pf input filter capacitors close to the ADT7411. 6. if the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. this will work up to about 6 to 12 feet. 7. for really long distances (up to 100 feet) use shielded twisted pair such as belden #8451 microphone cable. connect the twisted pair to d+ and d- and the shield
? 16 ? rev. prg preliminary technical data ADT7411 to gnd close to the ADT7411. leave the remote end of the shield unconnected to avoid ground loops. because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. when using long cables, the filter ca- pacitor may be reduced or removed. cable resistance can also introduce errors. 1 series resis- tance introduces about 0.5 o c error. temperature value format one lsb of the adc corresponds to 0.25 c. the adc can theoretically measure a temperature span of 255 c. the internal temperature sensor is guaranteed to a low value limit of -40 c. it is possible to measure the full temperature span using the external temperature sensor. the temperature data format is shown in table 3. the result of the internal or external temperature mea- surements is stored as 2 ? s complement format in the tem- perature value registers, and is compared with limits programmed into the internal or external high and low registers. table 3. temperature data format (internal and external temperature) temperature digital output -40 c 11 0110 0000 -25 c 11 1001 1100 -10 c 11 1101 1000 -0.25 c 11 1111 1111 0 c 00 0000 0000 +0.25 c 00 0000 0001 +10 c 00 0010 1000 +25 c 00 0110 0100 +50 c 00 1100 1000 +75 c 01 0010 1100 +100 c 01 1001 0000 +105 c 01 1010 0100 +125 c 01 1111 0100 temperature conversion formula: 1. positive temperature = adc code/4 2. negative temperature = (adc code* - 512)/4 *db9 is removed from the adc code interrupts the measured results from the internal temperature sen- sor, external temperature sensor, v dd pin and the ain inputs are compared with their t high /v high (greater than comparison) and t low /v low (greater than or equal to comparison) limits. an interrupt occurs if the measure- ment exceeds or equals the limit registers. these limits are stored in on-chip registers. please note that the limit registers are 8 bits long while the conversion results are 10 bits long. if the limits are not masked out then any out-of- limit comparisons generate flags that are stored in inter- rupt status 1 register (address = 00h) and interrupt status 2 register (address = 01h). one or more out-of limit results will cause the int/ int output to pull either high or low depending on the output polarity setting. it is good design practice to mask out interrupts for channels that are of no concern to the application. figure 11 shows the interrupt structure for the ADT7411. it gives a block diagram representation of how the various measurement channels affect the int/ int pin. ADT7411 registers the ADT7411 contains registers that are used to store the results of external and internal temperature measurements, v dd value measurements, analog input measurements, high and low temperature limits, supply voltage and analog input limits, configure multipurpose pins and generally control the device. a detailed description of these registers is given below. the register map is divided into registers of 8-bits long. each register has it ? s own indvidual address but some consist of data that is linked with other registers. these registers hold the 10-bit conversion results of measure- ments taken on the temperature, v dd and ain channels. for example, the 8 msbs of the v dd measurement are stored in register address 06h while the 2 lsbs are stored in register address 03h. the link involved between these types of registers is that when the lsb register is read first then the msb registers associated with that lsb register are locked to prevent any updates. to unlock these msb registers the user has only to read to any one of them which will have the affect of unlocking all previously locked msb registers. so for the example given above if register 03h was read first then msb registers 06h and 07h would be locked to prevent any updates to them. if register 06h was read then this register and register 07h would be subsequently unlocked. 1st read command lsb register output data lock associated msb registers figure 13. phase 1 of 10-bit read 2nd read command msb register output data unlock associated msb registers figure 14. phase 2 of 10-bit read if an msb register is read first, it ? s corresponding lsb register is not locked thus leaving the user with the option of just reading back 8 bits (msb) of a 10-bit conversion result. reading an msb register first does not lock up
ADT7411 ? 17 ? rev. prg preliminary technical data other msb registers and likewise reading an lsb register first does not lock up other lsb registers. table 4. list of ADT7411 registers rd/wr name power-on address default 00h interrupt status 1 00h 01h interrupt status 2 00h 02h reserved 03h internal temp & v dd lsbs 00h 04h external temp & ain 1-4 lsbs 00h 05h ain 5 - 8 lsbs 00h 06h v dd msbs 00h 07h internal temperature msbs 00h 08h external temp msbs/ 00h ain 1 msbs 09h ain 2 msbs 00h 0ah ain 3 msbs 00h 0bh ain 4 msbs 00h 0ch ain 5 msbs 00h 0dh ain 6 msbs 00h 0eh ain 7 msbs 00h 0fh ain 8 msbs 00h 10h-17h reserved 18h control config 1 08h 19h control config 2 00h 1ah control config 3 00h 1bh-1ch reserved 1dh interrupt mask 1 00h 1eh interrput mask 2 00h 1fh internal temp offset 00h 20h external temp offset 00h 21h reserved 22h reserved 23h v dd v high limit c7h 24h v dd v low limit 62h 25h internal t high limit 64h 26h internal t low limit c9h 27h external t high / ffh ain1 v high limits 28h external t low / 00h ain1 v low limits 29h-2ah reserved 2bh ain 2 v high limit ffh 2ch ain 2 v low limit 00h 2dh ain 3 v high limit ffh 2eh ain 3 v low limit 00h 2fh ain 4 v high limit ffh 30h ain 4 v low limit 00h 31h ain 5 v high limit ffh 32h ain 5 v low limit 00h 33h ain 6 v high limit ffh 34h ain 6 v low limit 00h 35h ain 7 v high limit ffh 36h ain 7 v low limit 00h 37h ain 8 v high limit ffh 38h ain 8 v low limit 00h 39h-4ch reserved 4dh device id 02h 4eh manufacturer ? s id 41h 4fh silicon revision 00h 50h-7eh reserved 00h 7 f spi lock status 00h 80-ffh reserved 00h interrupt status 1 register (read only) [add. = 00h] this 8-bit read only register reflects the status of some of the interrupts that can cause the int/ int pin to go ac- tive. this register is reset by a read operation provided that any out of limit event has been corrected. it is also reset by a software reset. table 5. interrupt status 1 register d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. bit function
? 18 ? rev. prg preliminary technical data ADT7411 d 0 1 when internal temp value exceeds t high limit. any internal temperature reading greater than the limit set will cause an out of limit event. d 1 1 when internal temp value exceeds t low limit. any internal temperature reading less than or equal to the limit set will cause an out of limit event. d 2 this status bit is linked to the configuration of pins 7 and 8. if configured for external temperature sensor then this bit is 1 when external temp value ex- ceeds t high limit. the default value for this limit register is -1 o c so any external temperature read- ing greater than the limit set will cause an out of limit event. if configured for ain1 and ain2 then this bit is 1 when ain1 input voltage exceeds v high or v low limits. d 3 1 when external temp value exceeds t low limit. the default value for this limit register is 0 o c so any external temperature reading less than or equal to the limit set will cause an out of limit event. d 4 1 indicates a fault (open or short) for the external temperature sensor. d 5 1 when ain2 voltage is greater than correspond- ing v high limit. 1 when ain2 voltage is less than or equal to cor- responding v low limit. d 6 1 when ain3 voltage is greater than correspond- ing v high limit. 1 when ain3 voltage is less than or equal to cor- responding v low limit. d 7 1 when ain4 voltage is greater than correspond- ing v high limit. 1 when ain4 voltage is less than or equal to cor- responding v low limit. interrupt status 2 register (read only) [add. = 01h] this 8-bit read only register reflects the status of the v dd and ain5-ain8 interrupts that can cause the int/ int pin to go active. this register is reset by a read operation provided that any out of limit event has been corrected. it is also reset by a software reset. table 6. interrupt status 2 register d7 d6 d5 d4 d3 d2 d1 d0 n/a n/a n/a 0* n/a n/a n/a n/a *default settings at power-up. bit function d 0 1 when ain5 voltage is greater than correspond- ing v high limit. 1 when ain5 voltage is less than or equal to cor- responding v low limit. d 1 1 when ain6 voltage is greater than correspond- ing v high limit. 1 when ain6 voltage is less than or equal to cor- responding v low limit. d 2 1 when ain7 voltage is greater than correspond- ing v high limit. 1 when ain7 voltage is less than or equal to cor- responding v low limit. d 3 1 when ain8 voltage is greater than correspond- ing v high limit. 1 when ain8 voltage is less than or equal to cor- responding v low limit. d 4 1 when v dd value is greater than corresponding v high limit. 1 when v dd is less than or equal to corresponding v low limit. d5:d7 reserved internal temperature value/v dd value register lsbs (read only) [add. = 03h] this internal temperature value and v dd value register is a 8-bit read-only register. it stores the two lsbs of the 10-bit temperature reading from the internal temperature sensor and also the two lsbs of the 10-bit supply voltage reading. table 7. internal temp/v dd lsbs d7 d6 d5 d4 d3 d2 d1 d0 n/a n/a n/a n/a v1 lsb t1 lsb n/a n/a n/a n/a 0* 0* 0* 0* *default settings at power-up. bit function d 0 lsb of internal temperature value d 1 b1 of internal temperature value d 2 lsb of v dd value d 3 b1 of v dd value external temperature value and analog inputs 1-4 register lsbs (read only) [add. = 04h] this is a 8-bit read-only register. bits d2 - d7 store the two lsbs of the analog inputs ain2 - ain4. bits d0 and d1 are used to store the two lsbs of either the external temperature value or ain1 input value. the type of input for d0 and d1 is selected by bits 1:2 of control configuration 1. table 8. external temperature & ain 1-4 lsbs d7 d6 d5 d4 d3 d2 d1 d0
ADT7411 ? 19 ? rev. prg preliminary technical data a4 a4 lsb a3 a3 lsb a2 a2 lsb t/a t/a lsb 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. bit function d 0 lsb of external temperature value or ain 1 value d 1 bit 1 of external temperature value or ain 1 value d 2 lsb of ain 2 value d 3 bit 1 of ain 2 value d 4 lsb of ain 3 value d 5 bit 1 of ain 3 value d 6 lsb of ain 4 value d 7 bit 1 of ain 4 value analog inputs 5-8 register lsbs (read only) [add. = 05h] this is a 8-bit read-only register. bits d0 - d7 store the two lsbs of the analog inputs ain5 - ain8. the msbs are stored in registers 0ch to 0fh. table 9. external temperature & ain 1-4 lsbs d7 d6 d5 d4 d3 d2 d1 d0 a8 a8 lsb a7 a7 lsb a6 a6 lsb a5 a5 lsb 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. bit function d 0 lsb of ain 5 value d 1 bit 1 of ain 5 value d 2 lsb of ain 6 value d 3 bit 1 of ain 6 value d 4 lsb of ain 7 value d 5 bit 1 of ain 7 value d 6 lsb of ain 8 value d 7 bit 1 of ain 8 value v dd value register msbs (read only) [add. = 06h] this 8-bit read only register stores the supply voltage value. the 8 msbs of the 10-bit value are stored in this register. table 10. v dd value msbs d7 d6 d5 d4 d3 d2 d1 d0 v9 v8 v7 v6 v5 v4 v3 v2 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. internal temperature value register msbs (read only) [add. = 07h] this 8-bit read only register stores the internal tempera- ture value from the internal temperature sensor in twos complement format. the 8 msbs of the 10-bit value are stored in this register. table 11. internal temperature value msbs d7 d6 d5 d4 d3 d2 d1 d0 t9 t8 t7 t6 t5 t4 t3 t2 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. external temperature value or analog input ain 1 register msbs (read only) [add. = 08h] this 8-bit read only register stores, if selected, the exter- nal temperature value or the analog input ain 1 value. selection is done in control configuration 1 register. the external temperature value is stored in twos complement format. the 8 msbs of the 10-bit value are stored in this register. table 12. external temperature value/analog inputs msbs d7 d6 d5 d4 d3 d2 d1 d0 t/a9 t/a8 t/a7 t/a6 t/a5 t/a4 t/a3 t/a2 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. ain 2 register msbs (read) [add. = 09h] this 8-bit read register contains the 8 msbs of the ain 2 analog input voltage word. the value in this register is combined with bits d2:3 of the external temperature value and analog inputs 1-4 register lsbs, address 04h, to give the full 10-bit conversion result of the analog value on the ain 2 pin. table 13. ain 2 msbs d7 d6 d5 d4 d3 d2 d1 d0 msb a8 a7 a6 a5 a4 a3 a2 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. ain 3 register msbs (read) [add. = 0ah] this 8-bit read register contains the 8 msbs of the ain 3 analog input voltage word. the value in this register is combined with bits d4:5 of the external temperature value and analog inputs 1-4 register lsbs, address 04h, to give the full 10-bit conversion result of the analog value on the ain 3 pin.
? 20 ? rev. prg preliminary technical data ADT7411 table 14. ain 3 msbs d7 d6 d5 d4 d3 d2 d1 d0 msb a8 a7 a6 a5 a4 a3 a2 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. ain 4 register msbs (read) [add. = 0bh] this 8-bit read register contains the 8 msbs of the ain 4 analog input voltage word. the value in this register is combined with bits d6:7 of the external temperature value and analog inputs 1-4 register lsbs, address 04h, to give the full 10-bit conversion result of the analog value on the ain 4 pin. table 15. ain 4 msbs d7 d6 d5 d4 d3 d2 d1 d0 msb a8 a7 a6 a5 a4 a3 a2 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. ain 5 register msbs (read) [add. = 0ch] this 8-bit read register contains the 8 msbs of the ain 5 analog input voltage word. the value in this register is combined with bits d0:1 of the analog inputs 5-8 regis- ter lsbs, address 05h, to give the full 10-bit conversion result of the analog value on the ain 5 pin. table 16. ain 5 msbs d7 d6 d5 d4 d3 d2 d1 d0 msb a8 a7 a6 a5 a4 a3 a2 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. ain 6 register msbs (read) [add. = 0dh] this 8-bit read register contains the 8 msbs of the ain 6 analog input voltage word. the value in this register is combined with bits d2:3 of the analog inputs 5-8 regis- ter lsbs, address 05h, to give the full 10-bit conversion result of the analog value on the ain 6 pin. table 17. ain 6 msbs d7 d6 d5 d4 d3 d2 d1 d0 msb a8 a7 a6 a5 a4 a3 a2 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. ain 7 register msbs (read) [add. = 0eh] this 8-bit read register contains the 8 msbs of the ain 7 analog input voltage word. the value in this register is combined with bits d4:5 of the analog inputs 5-8 regis- ter lsbs, address 05h, to give the full 10-bit conversion result of the analog value on the ain 7 pin. table 18. ain 7 msbs d7 d6 d5 d4 d3 d2 d1 d0 msb a8 a7 a6 a5 a4 a3 a2 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. ain 8 register msbs (read) [add. = 0fh] this 8-bit read register contains the 8 msbs of the ain 8 analog input voltage word. the value in this register is combined with bits d6:7 of the analog inputs 5-8 regis- ter lsbs, address 05h, to give the full 10-bit conversion result of the analog value on the ain 8 pin. table 19. ain 8 msbs d7 d6 d5 d4 d3 d2 d1 d0 msb a8 a7 a6 a5 a4 a3 a2 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. control configuration 1 register (read/ write) [add. = 18h] this configuration register is an 8-bit read/write register that is used to setup some of the operating modes of the ADT7411. table 20. control configuration 1 d7 d6 d5 d4 d3 d2 d1 d0 pd c6 c5 c4 c3 c2 c1 c0 0* 0* 0* 0* 1* 0* 0* 0* *default settings at power-up. bit function c0 this bit enables/disables conversions in round robin and single channel mode. ADT7411 powers up in round robin mode but monitoring is not initiated until this bit is set. default = 0. 0 = stop monitoring. 1 = start monitoring. c2:c1 selects between the two different analog inputs on pins 7 and 8. ADT7411 powers up with ain1 and ain2 selected. 00 ain1 and ain2 selected. 01 undefined. 10 external tdm selected. 11 undefined. c3 reserved. write 1 only to this bit. c4 reserved. write 0 only. c5 0 enable int/ int output 1 disable int/ int output c6 configures int/ int output polarity. 0 active low 1 active high
ADT7411 ? 21 ? rev. prg preliminary technical data p d power-down bit. setting this bit to 1 puts the ADT7411 into standby mode. in this mode the analog circuitry is fully powered down, but serial interface is still operational. to power up the part again just write 0 to this bit. control configuration 2 register (read/ write) [add. = 19h] this configuration register is an 8-bit read/write register that is used to setup some of the operating modes of the ADT7411. table 21. control configuration 2 d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. bit function c3:0 in single channel mode these bits select between v dd , the internal temperature sensor, external temperature sensor/ain1, ain2 to ain8 for conversion. default is v dd . 0000 = v dd 0001 = internal temperature sensor. 0010 = external temperature sensor/ain1 (bits c1:c2 of control configuration 1 affect this selection) 0011 = ain2 0100 = ain3 0101 = ain4 0110 = ain5 0111 = ain6 1000 = ain7 1001 = ain8 1010 - 1111 = reserved. c4 selects between single channel and round robin conversion cycle. default is round robin. 0 = round robin. 1 = single channel. c5 default condition is to average every measure- ment on all channels 16 times. this bit disables this averaging. c hannels affected are tempera- ture, analog inputs and v dd . 0 = enable averaging. 1 = disable averaging. c6 smbus timeout on the serial clock puts a 25ms limit on the pulse width of the clock. ensures that a fault on the master scl does not lock up the sda line. 0 = disable smbus timeout. 1 = enable smbus timeout. c7 software reset. setting this bit to a 1 causes a software reset. all registers will reset to their default settings. control configuration 3 register (read/ write) [add. = 1ah] this configuration register is an 8-bit read/write register that is used to setup some of the operating modes of the ADT7411. table 22. control configuration 3 d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 0* 0* 0* 0* 1* 0* 0* 0* *default settings at power-up. bit function c0 selects between fast and normal adc conver- sion speeds. 0 = adc clock at 1.4 khz. 1 = adc clock at 22.5 khz. analog filters are disabled. c1:2 reserved. only write 0 ? s. c3 reserved. write only 1 to this bit. c4 selects the adc reference to be either internal v ref or v dd for analog inputs. 0 = int v ref 1 = v dd c5-c7 reserved. only write 0 ? s. interrupt mask 1 register (read/write) [add. = 1dh] this mask register is an 8-bit read/write register that can be used to mask out any interrupts that can cause the int/ int pin to go active. table 23. interrupt mask 1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. bit function d 0 0 = enable internal t high interrupt. 1 = disable internal t high interrupt. d 1 0 = enable internal t low interrupt. 1 = disable internal t low interrupt. d 2 0 = enable external t high interrupt or ain1 interrupt. 1 = disable external t high interrupt or ain1 interrupt. d 3 0 = enable external t low interrupt. 1 = disable external t low interrupt. d 4 0 = enable external temperature fault interrupt. 1 = disable external temperature fault interrupt.
? 22 ? rev. prg preliminary technical data ADT7411 d 5 0 = enable ain2 interrupt. 1 = disable ain2 interrupt. d 6 0 = enable ain3 interrupt. 1 = disable ain3 interrupt. d 7 0 = enable ain4 interrupt. 1 = disable ain4 interrupt. interrupt mask 2 register (read/write) [add. = 1eh] this mask register is an 8-bit read/write register that can be used to mask out any interrupts that can cause the int/ int pin to go active. table 24. interrupt mask 2 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. bit function d 0 0 = enable ain5 interrupt. 1 = disable ain5 interrupt. d 1 0 = enable ain6 interrupt. 1 = disable ain6 interrupt. d 2 0 = enable ain7 interrupt. 1 = disable ain7 interrupt. d 3 0 = enable ain8 interrupt. 1 = disable ain8 interrupt. d 4 0 = enable v dd interrupts. 1 = disable v dd interrupts. d5:d7 reserved. only write 0 ? s. internal temperature offset register (read/write) [add. = 1fh] this register contains the offset value for the internal temperature channel. a 2's complement number can be written to this register which is then 'added' to the mea- sured result before it is stored or compared to limits. in this way a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. from a software point of view this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change. as it is an 8-bit register the temperature resolu- tion is 1 o c. table 25. internal temperature offset d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. external temperature offset register (read/write) [add. = 20h] this register contains the offset value for the internal temperature channel. a 2's complement number can be written to this register which is then 'added' to the mea- sured result before it is stored or compared to limits. in this way a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. from a software point of view this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change. as it is an 8-bit register the temperature resolu- tion is 1 o c. table 26. external temperature offset d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. v dd v high limit register (read/write) [add. = 23h] this limit register is an 8-bit read/write register which stores the v dd upper limit that will cause an interrupt and activate the int/ int output (if enabled). for this to happen the measured v dd value has to be greater than the value in this register. default value is 5.46 v. table 27. v dd v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 0* 0* 0* 1* 1* 1* *default settings at power-up. v dd v low limit register (read/write) [add. = 24h] this limit register is an 8-bit read/write register which stores the v dd lower limit that will cause an interrupt and activate the int/ int output (if enabled). for this to happen the measured v dd value has to be less than or equal to the value in this register. default value is 2.7 v. table 28. v dd v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 1* 1* 0* 0* 0* 1* 0* *default settings at power-up. internal t high limit register (read/write) [add. = 25h] this limit register is an 8-bit read/write register which stores the 2 ? s complement of the internal temperature upper limit that will cause an interrupt and activate the int/ int output (if enabled). for this to happen the measured internal temperature value has to be greater than the value in this register. as it is an 8-bit register the temperature resolution is 1 o c. default value is +100 o c.
ADT7411 ? 23 ? rev. prg preliminary technical data table 29. internal t high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 1* 1* 0* 0* 1* 0* 0* *default settings at power-up. internal t low limit register (read/write) [add. = 26h] this limit register is an 8-bit read/write register which stores the 2 ? s complement of the internal temperature lower limit that will cause an interrupt and activate the int/ int output (if enabled). for this to happen the measured internal temperature value has to be more negative than or equal to the value in this register. as it is an 8-bit register the temperature resolution is 1 o c. de- fault value is -55 o c. table 30. internal t low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 0* 0* 1* 0* 0* 1* *default settings at power-up. external t high / ain1 v high limit register (read/write) [add. = 27h] if pins 7 and 8 are configured for the external temperature sensor then this limit register is an 8-bit read/write regis- ter which stores the 2 ? s complement of the external tem- perature upper limit that will cause an interrupt and activate the int/ int output (if enabled). for this to happen the measured external temperature value has to be greater than the value in this register. as it is an 8-bit register the temperature resolution is 1 o c. default value = -1 o c. if pins 7 and 8 are configured for ain1 and ain2 single- ended inputs then this limit register is an 8-bit read/write register which stores the ain1 input upper limit that will cause an interrupt and activate the int/ int output (if enabled). for this to happen the measured ain1 value has to be greater than the value in this register. as it is an 8- bit register the resolution is four times less than the reso- lution of the 10-bit adc. as the power-up default settings for pins 7 and 8 is ain1 and ain2 single-ended inputs then the default value for this limit register is fullscale voltage. table 31. ain1 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 1* 1* 1* 1* 1* 1* *default settings at power-up. external t low / ain1 v low limit register (read/write) [add. = 28h] if pins 7 and 8 are configured for the external temperature sensor then this limit register is an 8-bit read/write regis- ter which stores the 2 ? s complement of the external tem- perature lower limit that will cause an interrupt and activate the int/ int output (if enabled). for this to happen the measured external temperature value has to be more negative than or equal to the value in this regis- ter. as it is an 8-bit register the temperature resolution is 1 o c. default value = 0 o c. if pins 7 and 8 are configured for ain1 and ain2 single- ended inputs then this limit register is an 8-bit read/write register which stores the ain1 input lower limit that will cause an interrupt and activate the int/ int output (if enabled). for this to happen the measured ain1 value has to be less than or equal to the value in this register. as it is an 8-bit register the resolution is four times less than the resolution of the 10-bit adc. as the power-up default settings for pins 7 and 8 is ain1 and ain2 single-ended inputs then the default value for this limit register is 0 v. table 32. ain1 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. ain2 v high limit register (read/write) [add. = 2bh] this limit register is an 8-bit read/write register which stores the ain2 input upper limit that will cause an inter- rupt and activate the int/ int output (if enabled). for this to happen the measured ain2 value has to be greater than the value in this register. as it is an 8-bit register the resolution is four times less than the resolution of the 10- bit adc. default value is fullscale voltage. table 33. ain2 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 1* 1* 1* 1* 1* 1* *default settings at power-up. ain2 v low limit register (read/write) [add. = 2ch] this limit register is an 8-bit read/write register which stores the ain2 input lower limit that will cause an inter- rupt and activate the int/ int output (if enabled). for this to happen the measured ain2 value has to be less than or equal to the value in this register. as it is an 8-bit register the resolution is four times less than the resolution of the 10-bit adc. default value is 0 v. table 34. ain2 v low limit d7 d6 d5 d4 d3 d2 d1 d0
? 24 ? rev. prg preliminary technical data ADT7411 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. ain3 v high limit register (read/write) [add. = 2dh] this limit register is an 8-bit read/write register which stores the ain3 input upper limit that will cause an inter- rupt and activate the int/ int output (if enabled). for this to happen the measured ain3 value has to be greater than the value in this register. as it is an 8-bit register the resolution is four times less than the resolution of the 10- bit adc. default value is fullscale voltage. table 35. ain3 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 1* 1* 1* 1* 1* 1* *default settings at power-up. ain3 v low limit register (read/write) [add. = 2eh] this limit register is an 8-bit read/write register which stores the ain3 input lower limit that will cause an inter- rupt and activate the int/ int output (if enabled). for this to happen the measured ain3 value has to be less than or equal to the value in this register. as it is an 8-bit register the resolution is four times less than the resolution of the 10-bit adc. default value is 0 v. table 36. ain3 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. ain4 v high limit register (read/write) [add. = 2fh] this limit register is an 8-bit read/write register which stores the ain4 input upper limit that will cause an inter- rupt and activate the int/ int output (if enabled). for this to happen the measured ain4 value has to be greater than the value in this register. as it is an 8-bit register the resolution is four times less than the resolution of the 10- bit adc. default value is fullscale voltage. table 37. ain4 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 1* 1* 1* 1* 1* 1* *default settings at power-up. ain4 v low limit register (read/write) [add. = 30h] this limit register is an 8-bit read/write register which stores the ain4 input lower limit that will cause an inter- rupt and activate the int/ int output (if enabled). for this to happen the measured ain4 value has to be less than or equal to the value in this register. as it is an 8-bit register the resolution is four times less than the resolution of the 10-bit adc. default value is 0 v. table 38. ain4 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. ain5 v high limit register (read/write) [add. = 31h] this limit register is an 8-bit read/write register which stores the ain5 input upper limit that will cause an inter- rupt and activate the int/ int output (if enabled). for this to happen the measured ain5 value has to be greater than the value in this register. as it is an 8-bit register the resolution is four times less than the resolution of the 10- bit adc. default value is fullscale voltage. table 39. ain5 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 1* 1* 1* 1* 1* 1* *default settings at power-up. ain5 v low limit register (read/write) [add. = 32h] this limit register is an 8-bit read/write register which stores the ain5 input lower limit that will cause an inter- rupt and activate the int/ int output (if enabled). for this to happen the measured ain5 value has to be less than or equal to the value in this register. as it is an 8-bit register the resolution is four times less than the resolution of the 10-bit adc. default value is 0 v. table 40. ain5 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. ain6 v high limit register (read/write) [add. = 33h] this limit register is an 8-bit read/write register which stores the ain3 input upper limit that will cause an inter- rupt and activate the int/ int output (if enabled). for this to happen the measured ain6 value has to be greater than the value in this register. as it is an 8-bit register the resolution is four times less than the resolution of the 10- bit adc. default value is fullscale voltage. table 41. ain6 v high limit d7 d6 d5 d4 d3 d2 d1 d0
ADT7411 ? 25 ? rev. prg preliminary technical data d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 1* 1* 1* 1* 1* 1* *default settings at power-up. ain6 v low limit register (read/write) [add. = 34h] this limit register is an 8-bit read/write register which stores the ain6 input lower limit that will cause an inter- rupt and activate the int/ int output (if enabled). for this to happen the measured ain6 value has to be less than or equal to the value in this register. as it is an 8-bit register the resolution is four times less than the resolution of the 10-bit adc. default value is 0 v. table 42. ain6 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. ain7 v high limit register (read/write) [add. = 35h] this limit register is an 8-bit read/write register which stores the ain7 input upper limit that will cause an inter- rupt and activate the int/ int output (if enabled). for this to happen the measured ain7 value has to be greater than the value in this register. as it is an 8-bit register the resolution is four times less than the resolution of the 10- bit adc. default value is fullscale voltage. table 43. ain7 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 1* 1* 1* 1* 1* 1* *default settings at power-up. ain7 v low limit register (read/write) [add. = 36h] this limit register is an 8-bit read/write register which stores the ain7 input lower limit that will cause an inter- rupt and activate the int/ int output (if enabled). for this to happen the measured ain7 value has to be less than or equal to the value in this register. as it is an 8-bit register the resolution is four times less than the resolution of the 10-bit adc. default value is 0 v. table 44. ain7 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. ain8 v high limit register (read/write) [add. = 37h] this limit register is an 8-bit read/write register which stores the ain8 input upper limit that will cause an inter- rupt and activate the int/ int output (if enabled). for this to happen the measured ain8 value has to be greater than the value in this register. as it is an 8-bit register the resolution is four times less than the resolution of the 10- bit adc. default value is fullscale voltage. table 45. ain8 v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 1* 1* 1* 1* 1* 1* *default settings at power-up. ain8 v low limit register (read/write) [add. = 38h] this limit register is an 8-bit read/write register which stores the ain8 input lower limit that will cause an inter- rupt and activate the int/ int output (if enabled). for this to happen the measured ain8 value has to be less than or equal to the value in this register. as it is an 8-bit register the resolution is four times less than the resolution of the 10-bit adc. default value is 0 v. table 46. ain8 v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. device id register (read only) [add. = 4dh] this 8-bit read only register gives an unique identification number for this part. ADT7411 = 02h. manufacturer?s id register (read only) [add. = 4eh] this register contains the manufacturers identification number. adi ? s is 41h. silicon revision register (read only) [add. = 4fh] this register is divided into the four lsbs representing the stepping and the four msbs representing the version. the stepping contains the manufacturers code for minor revi- sions or steppings to the silicon. the version is the ADT7411 version number. the ADT7411 ? s version num- ber is 0100b (4h). spi lock status register (read only) [add. = 7fh] bit d0 (lsb) of this read only register indicates whether the spi interface is locked or not. writing to this register will cause the device to malfunction. default value is 00h. 0 = i 2 c interface 1 = spi interface selected and locked. ADT7411 serial interface there are two serial interfaces that can be used on this part, i 2 c and spi. the device will power up with the se- rial interface in i 2 c mode but it is not locked into this mode. to stay in i 2 c mode it is recommended that the
? 26 ? rev. prg preliminary technical data ADT7411 user ties the cs line to either v cc or gnd. it is not pos- sible to lock the i 2 c mode but it is possible to select and lock the spi mode. to select and lock the interface into the spi mode, a number of pulses must be sent down the cs (pin 4) line. the following section describes how this is done. once the spi communication protocol has been locked in, it cannot be unlocked while the device is still powered up. bit d0 of spi lock status register (address = 7fh) is set to 1 when a successful spi interface lock has been acomplished. to reset the serial interface the user must power down the part and power up again. a software reset does not reset the serial interface. serial interface selection the cs line controls the selection between i 2 c and spi. figure 16 shows the selection process necessary to lock the spi interface mode. if the user wants to communicate to the ADT7411 using the spi protocol, send three pulses down the cs line as shown in figure 16(a) and 16(b). on the third rising edge (marked as c in figure 16) the part selects and locks the spi interface. the user is now limited to communicating to the device using the spi protocol. as per most spi standards, the cs line must be low dur- ing every spi communication to the ADT7411 and high all other times. typical examples of how to connect up the dual interface as i 2 c or spi is shown in figures 15(a) and 15(b). v dd v dd cs sda scl ADT7411 add i 2 c address = 1001 000 figure 15(a). typical i 2 c interface connection cs din sclk ADT7411 dout spi framing edge lock and select spi figure 15(b). typical spi interface connection the following sections describe in detail how to use the i 2 c and spi protocols associated with the ADT7411. i 2 c serial interface like all i 2 c-compatible devices, the ADT7411 has an 7- bit serial address. the four msbs of this address for the figure 16(a). serial interface - selecting and locking spi protocol figure 16(b). serial interface - selecting and locking spi protocol cs (start high) spi locked on 3 rd rising edge a b c spi framing edge spi locked on 3 rd rising edge cs (start low) a b c spi framing edge
ADT7411 ? 27 ? rev. prg preliminary technical data ADT7411 are set to 1001. the three lsbs are set by pin 11, add. the add pin can be configured three ways to give three different address options; low, floating and high. setting the add pin low gives a serial bus address of 1001 000, leaving it floating gives the address 1001 010 and setting it high gives the address 1001 011. there is an enable/disable bit for the smbus timout. when this is enabled the smbus will timeout after 25 ms of no activity. to enable it, set bit 6 of control configu- ration 2 register. the power-up default is with the smbus timeout disabled. the ADT7411 supports smbus packet error checking (pec) and it ? s use is optional. it is triggered by supplying the extra clocks for the pec byte. the pec is calculated using crc-8. the frame clock sequence (fcs) con- forms to crc-8 by the polynominal : c(x) = x 8 + x 2 + x 1 + 1 consult smbus specification (www.smbus.org) for more information. the serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, defined as a high to low transition on the serial data line sda whilst the serial clock line scl remains high. this indicates that an address/data stream will follow. all slave peripherals connected to the serial bus respond to the start condition, and shift in the next 8 bits, consisting of a 7-bit address (msb first) plus a r/ w bit, which determines the di- rection of the data transfer, i.e. whether data will be written to or read from the slave device. the peripheral whose address corresponds to the trans- mitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. all other devices on the bus now remain idle whilst the selected device waits for data to be read from or written to it. if the r/ w bit is a 0 then the master will write to the slave device. if the r/ w bit is a 1 the master will read from the slave de- vice. 2. data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an acknowledge bit from the receiver of data. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be inter- preted as a stop signal. 3. when all data bytes have been read or written, stop conditions are established. in write mode, the master will pull the data line high during the 10th clock pulse to assert a stop condition. in read mode, the mas- ter device will pull the data line high during the low period before the 9th clock pulse. this is known as no acknowledge. the master will then take the data line figure 18. i 2 c - writing to the address pointer register followed by a single byte of data to the selected register r/ w 1 scl sda 0 0 1 a2 a1 a0 p7 p6 p5 p4 p3 p2 p1 p0 ack. by adt7516/17/18 start by master fra m e 1 serial bus address byte frame 2 address pointer register byte 191 ack. by adt7516/17/18 9 d7 d6 d5 d4 d3 d2 d1 d0 ack. by adt7516/17/18 stop by master fra m e 3 data byte 19 scl (continued) sda (continued) figure 17. i 2 c - writing to the address pointer register to select a register for a subsequent read operation r/ w 1 scl sda 001a2a1a0 p7p6p5p4p3p2p1p0 ack. by adt7516/17/18 stop by master start by master frame 1 serial bus address byte frame 2 address pointer register byte 191 ack. by adt7516/17/18 9
? 28 ? rev. prg preliminary technical data ADT7411 low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of opera- tion is determined at the beginning and cannot subse- quently be changed without starting a new operation. the i 2 c address set up by the add pin is not latched by the device until after this address has been sent twice. on the 8 th scl cycle of the second valid communication, the serial bus address is latched in. this is the scl cycle directly after the device has seen it ? s own i 2 c serial bus address. any subsequent changes on this pin will have no affect on the i 2 c serial bus address. writing to the ADT7411 depending on the register being written to, there are two different writes for the ADT7411. it is not possible to do a block write to this part i.e no i 2 c auto-increment. writing to the address pointer register for a subsequent read. in order to read data from a particular register, the ad- dress pointer register must contain the address of that register. if it does not, the correct address must be written to the address pointer register by performing a single- byte write operation, as shown in figure 17. the write operation consists of the serial bus address followed by the address pointer byte. no data is written to any of the data registers. a read operation is then performed to read the register. writing data to a register. all registers are 8-bit registers so only one byte of data can be written to each register. writing a single byte of data to one of these read/write registers consists of the serial bus address, the data register address written to the address pointer register, followed by the data byte written to the selected data register. this is illustrated in figure 18. to write to a different register, another start or repeated start is required. if more than one byte of data is sent in one communication operation, the ad- figure 19. i 2 c - reading a single byte of data from a selected register sda no ack. by master start by master frame 1 serial bus address byte frame 2 single data byte from adt7516/17/18 ack. by adt7516/17/18 191 9 d7 d6 d5 d4 d3 d2 d1 d0 r/ w a0 a1 a2 1 0 1 scl stop by master 0 figure 20. spi - writing to the address pointer register followed by a single byte of data to the selected register d7 d in d6 d5 d4 d3 d2 d1 d6 d5 d4 d3 d2 d1 d0 d0 d7 sclk start write command register address 18 1 8 cs stop data byte d7 d6 d5 d4 d3 d2 d1 d0 d in (continued) 1 8 sclk (continued) cs (continued)
ADT7411 ? 29 ? rev. prg preliminary technical data d7 d in d6 d5 d4 d3 d2 d1 d6 d5 d4 d3 d2 d1 d0 d0 d7 sclk start write command register address 18 1 8 cs stop dressed register will be repeately loaded until the last data byte has been sent. reading data from the ADT7411 reading data from the ADT7411 is done in a one byte operation. reading back the contents of a register is shown in figure 19. the register address previously hav- ing been set up by a single byte write operation to the address pointer register. if you want to read from another register then you will have to write to the address pointer register again to set up the relevant register address. thus block reads are not possible i.e. no i 2 c auto-increment. spi serial interface the spi serial interface of the ADT7411 consists of four wires, cs , sclk, din and dout. the cs is used to select the device when more than one device is connected to the serial clock and data lines. the cs is also used to distinguish between any two seperate serial communica- tions, reference figure 24 for graphical explanation. the sclk is used to clock data in and out of the part. the din line is used to write to the registers and the dout line is used to read data back from the registers. the part operates in a slave mode and requires an exter- nally applied serial clock to the sclk input. the serial interface is designed to allow the part to be interfaced to systems that provide a serial clock that is synchronized to the serial data. figure 22. spi - reading a single byte of data from a selected register figure 21. spi - writing to the address pointer register to select a register for a subsequent read operation d7 d in d6 d5 d4 d3 d2 d1 x x x x x x x d0 x sclk start read command data byte 1 18 1 8 cs x d out xx x x x x d6 d5 d4 d3 d2 d1 d0 xd7 stop there are two types of serial operations, a read and a write. command words are used to distinguish between a read and a write operation. these command words are given in table 47. address auto-increment is possible in spi mode. table 47. spi command words write read 90h (1001 0000) 91h (1001 0001) write operation figure 20 shows the timing diagram for a write operation to the ADT7411. data is clocked into the registers on the rising edge of sclk. when the cs line is high the din and dout lines are in three-state mode. only when the cs goes from a high to a low does the part accept any data on the din line. in spi mode the address pointer register is capable of auto-incrementing to the next regis- ter in the register map without having to load the address pointer register each time. in figure 20 the register ad- dress portion of the diagram gives the first register that will be written to. subsequent data bytes will be written into sequential writable registers. thus after each data byte has been written into a register, the address pointer register auto increments it ? s value to the next available register. the address pointer register will auto-increment
? 30 ? rev. prg preliminary technical data ADT7411 cs spi read operation write operation figure 24. spi - correct use of cs during spi communication figure 23. spi - reading a two bytes of data from two sequential registers d7 d in d6 d5 d4 d3 d2 d1 x x x x x x x d0 x sclk start read command data byte 1 18 1 8 cs x d out xx x x x x d6 d5 d4 d3 d2 d1 d0 xd7 stop data byte 2 x x x x x x x x d in (continued) 1 8 sclk (continued) cs (continued) d7 d6 d5 d4 d3 d2 d1 d0 d out (continued) from 00h to 3fh and will loop back to start all over again at 00h when it reaches 3fh. read operation figures 21 to 23 show the timing diagrams necessary to accomplish correct read operations. to read back from a register you first have to write to the address pointer reg- ister with the address of the register you wish to read from. this operation is shown in figure 21. figure 22 shows the procedure for reading back a single byte of data. the read command is first sent to the part during the first 8 clock cycles, during the following 8 clock cycles the data contained in the register selected by the address pointer register is outputted onto the dout line. data is outputted onto the dout line on the falling edge of sclk. figure 23 shows the procedure when reading data from two sequential registers. multiple data reads are possible in spi interface mode as the address pointer register is auto-incremental. the address pointer regis- ter will auto-increment from 00h to 3fh and will loop back to start all over again at 00h when it reaches 3fh. smbus/spi int/ int the ADT7411 int /int output is an interrupt line for devices that want to trade their ability to master for an extra pin. the ADT7411 is a slave only device and uses the smbus/spi int /int to signal the host device that it wants to talk. the smbus/spi int /int on the ADT7411 is used as an over/under limit indicator. the int /int pin has an open-drain configuration which allows the outputs of several devices to be wired-and together when the int /int pin is active low. use c6 of the control configuration 1 register to set the active polarity of the int /int output. the power-up default is active low. the int /int output can be disabled or en- abled by setting c5 of control configuration 1 register to a 1 or 0 respectively.
ADT7411 ? 31 ? rev. prg preliminary technical data the int /int output becomes active when either the internal temperature value, the external temperature value, v dd value or any of the ain input values exceed the values in their corresponding t high /v high or t low / v low registers. the int /int output goes inactive again when a conversion result has the measured value back within the trip limits. the two interrupt status registers show which event caused the int/ int pin to go active. the int/ int output requires an external pull-up resis- tor. this can be connected to a voltage different from v dd provided the maximum voltage rating of the int/ int output pin is not exceeded. the value of the pull-up resis- tor depends on the application, but should be as large enough to avoid excessive sink currents at the int/ int output, which can heat the chip and affect the temperature reading.
? 32 ? rev. prg preliminary technical data ADT7411 outline dimensions (dimensions shown in inches and mm ) 16-lead qsop package ( rq-16 ) 16 9 8 1 0.19 7 (5.00) 0.18 9 (4.80) 0.24 4 (6.20) 0.22 8 (5.79) pin 1 0.157 (3.99) 0.150 (3.81) seating plane 0.010 (0.25) 0.004 (0.10) 0.012 (0.30 ) 0.008 (0.20 ) 0.025 (0.64) bsc 0.059 (1.50) max 0.069 (1.75) 0.053 (1.35) 0.010 (0.20) 0.007 (0.18) 8 o 0 o

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